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ISL6413
Data Sheet October 2003 FN9129
PRELIMINARY
Triple Output Regulator with Single Synchronous Buck and Dual LDO
The ISL6413 is a highly integrated triple output regulator which provides a single chip solution for wireless chipset power management. The device integrates high efficiency synchronous buck regulator with two ultra low noise LDO regulators. The IC accepts an input voltage range of 3.0V to 3.6V and provides three regulated output voltages: 1.8V (PWM), 2.84V (LDO1), and another ultra-clean 2.84V (LDO2). The Synchronous current mode PWM regulator with integrated N- and P-channel power MOSFET provides preset 1.8V for BBP/MAC core supply. Synchronous rectification with internal MOSFETs is used to achieve higher efficiency and reduced number of external components. Operating frequency is typically 750kHz allowing the use of smaller inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500kHz to 1MHz. The PG_PWM output indicates loss of regulation on PWM output. The ISL6413 also has two LDO regulators which use an internal PMOS transistor as the pass device. LDO2 features ultra low noise that does not typically exceed 30V RMS to aid VCO stability. The EN_LDO pin controls LDO1 and LDO2 outputs. The ISL6413 also integrates a RESET function, which eliminates the need for additional RESET IC required in WLAN applications. The IC asserts a RESET signal whenever the VIN supply voltage drops below a preset threshold, keeping it asserted for at least 25ms after VIN has risen above the reset threshold. The PG_LDO output indicates loss of regulation on either of the two LDO outputs. Other features include over current protection for all three outputs and thermal shutdown. High integration and the thin Quad Flat No-lead (QFN) package makes ISL6413 an ideal choice to power many of today's small form factor industry standard wireless cards such as PCMCIA, mini-PCI and Cardbus-32.
Features
* Fully Integrated Synchronous Buck Regulator + Dual LDO * High Output Current (For QFN package) - PWM, 1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA - LDO1, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA - LDO2, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA * Ultra-Compact DC-DC Converter Design * Stable with Small Ceramic Output Capacitors * High conversion efficiency * Low Shutdown supply current * Ultra-Low Dropout Voltage for LDOs - LDO1, 2.84V. . . . . . . . . . . . . . . 125mV (typ.) at 300mA - LDO2, 2.84V. . . . . . . . . . . . . . . 100mV (typ.) at 200mA * Ultra-Low Output Voltage Noise - <30VRMS (typ.) for LDO2 (VCO Supply) * PG_LDO, PG_PWM and PG_PWM outputs * Extensive circuit protection and monitoring features - Over voltage protection - Over current protection - Shutdown - Thermal Shutdown * Integrated RESET output for microprocessor reset * Proven Reference Design for Total WLAN System Solution * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - Near Chip-Scale Package Footprint Improves PCB Efficiency and Is Thinner in Profile
Applications
* WLAN Cards - PCMCIA, Cardbus32, MiniPCI Cards - Compact Flash Cards * Liberty Chipset * Hand-Held Instruments
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # ISL6413IR -40 to 85 24 Ld QFN L24.4x4B
Related Literature
* TB363 - Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) * TB389 - PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6413 Pinout
ISL6413 (QFN) TOP VIEW
SGND PGND 20 PVCC GND 19 18 VOUT 17 CC2 16 VOUT2 15 GND_LDO 14 VOUT1 13 CC1 7 RESET 8 CT 9 VIN_LDO 10 VIN_LDO 11 RESET 12 EN_LDO L1 10H 0.1F SGND PGND PVCC GND VIN LX 1.8V C7 10F 19 18 17 16 ISL6413 15 14 13 7 RESET CT 8 VIN_LDO 9 10 VIN_LDO 11 RESET 12 EN_LDO VOUT CC2 VOUT2 GND_LDO VOUT1 CC1 C2 C3 33nF 10F C4 10F 2.84V C6 33nF 2.84V
VIN
24 PG_PWM PG_PWM SYNC NC EN_PWM PG_LDO 1 2 3 4 5 6
23
22
Typical Application Schematic
3.3V C10 10F C8 C9 1.0F
R1
10K PG_PWM PG_PWM SYNC NC 1 2 3 4 5 6
24
23
22
21
LX 21
20
3.3V
EN R3 10K PG_LDO
C1 10nF
3.3V C5 4.7F
NOTE: All capacitors are ceramic.
2
ISL6413 Functional Block Diagram
Gm CT RESET RESET RESET BAND GAP REF 1.2V WINDOW COMP. VIN_LDO VIN_LDO + LDO1 OUT1
PG_LDO
POR
POR
VIN_LDO CONTROL LOGIC EN_LDO
EN Gm
CC1 CC2
GND_LDO THERMAL SHUTDOWN 150oC
+ LDO2 WINDOW COMP. OUT2
VIN CURRENT SENSE SOFT START SLOPE COMPENSATION EN EA GM PWM OVERCURRENT, OVERVOLTAGE LOGIC
PVCC
SGND
GATE DRIVE
LX
VOUT
COMPENSATION PGND
750kHz OSCILLATOR ANTI-RINGING POWER GOOD PWM VOUT VIN
UVLO
ZERO CURRENT DETECT
GND
PWM REFERENCE 0.45V VOUT SYNC EN PG_PWM PG_PWM
3
ISL6413
Absolute Maximum Ratings (Note 1)
Supply Voltage VIN, PVCC, VIN _LDO. . . . . . . . GND -0.3V to +5.0V ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBDV
Thermal Information
Thermal Resistance JA (oC/W) JC (oC/W) QFN Package (Notes 1, 2). . . . . . . . . . 40 5 Maximum Junction Temperature (Plastic Package) -55oC to 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Operating Temperature Range ISL6413IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Operating Conditions
Temperature Range ISL6413I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY Supply Voltage Range Input UVLO Threshold
Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V, Compensation Capacitors = 33nF for LDO1 and LDO2. TA = 25oC. (Note 2) TEST CONDITIONS MIN TYP MAX UNITS
VIN, PVCC, VIN _LDO VTR VTF
3.0 2.55 2.5 -
3.3 2.62 2.55 0.9 1.9 15 20 1.0 1.5 150 20
3.6 2.66 2.59 1.1 2.5 20 25 1.5 2.0 25
V V V mA mA A A A A
oC oC
Operating Supply Current (Note 3)
Device active, but not switching VIN = VIN_LDO = PVCC = 3.3V fSW = 750kHz, COUT = 10F, IL = 0mA
Shutdown Supply Current
EN_PWM = EN_LDO = GND, TA = 25oC EN_PWM = EN_LDO = GND, TA = 85oC EN_PWM = EN_LDO = GND/VIN, TA = 25oC EN_PWM = EN_LDO = GND/VIN, TA = 85oC Rising Threshold
Input Bias Current
Thermal Shutdown Temperature (Note 6) Thermal Shutdown Hysteresis (Note 6) SYNCHRONOUS BUCK PWM REGULATOR Output Voltage Output Voltage Accuracy Line Regulation Maximum Output Current Peak Output Current Limit PMOS rDS(ON) NMOS rDS(ON) Efficiency Soft-Start Time OSCILLATOR Oscillator Frequency Frequency Synchronization Range (fSYNC) SYNC High Level Input Voltage SYNC Low Level Input Voltage
IOUT = 3mA to 400mA, TA = -40oC to 85oC IO = 10mA, VIN = VIN_LDO = PVCC = 3.0V to 3.6V -2.0 -0.5 400 600 IOUT = 200mA IOUT = 200mA IOUT = 200mA, VIN = 3.3V 4096 Clock Cycles @ 750kHz -
1.8 300 225 93 5.5
2.0 0.5 900 -
V % % mA mA m m % ms
TA = -40oC to +85oC Clock signal on SYNC pin
620 500 2.3 -
750 -
860 1000 1.0
kHz kHz V V
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ISL6413
Electrical Specifications
PARAMETER Sync Input Leakage Current Duty Cycle of External Clock Signal (Note 6) PG_PWM Rising Threshold Falling Threshold LDO1 SPECIFICATIONS Output Voltage Output Voltage Accuracy Maximum Output Current (Note 6) Output Current Limit (Note 6) Dropout Voltage (Note 4) Line Regulation Load Regulation Output Voltage Noise (Note 6) IOUT = 300mA VIN = 3.0V to 3.6V, IOUT = 10mA IOUT = 10mA to 300mA 10Hz < f < 100kHz, IOUT = 10mA COUT = 2.2F COUT = 10F LDO2 SPECIFICATIONS Output Voltage Output Voltage Accuracy Maximum Output Current (Note 6) Output Current Limit (Note 6) Dropout Voltage (Note 4) Line Regulation Load Regulation Output Voltage Noise (Note 6) IOUT = 200mA VIN = 3.0V to 3.6V, IOUT = 10mA IOUT = 10mA to 200mA 10Hz < f < 100kHz, IOUT = 10mA COUT = 2.2F COUT = 10F ENABLE (EN_PWM and (EN_LDO) EN High Level Input Voltage EN Low Level Input Voltage RESET BLOCK SPECIFICATIONS RESET Rising Threshold RESET Falling Threshold RESET Threshold Hysteresis RESET Current Source RESET/RESET Active Timeout Period (Note 5) POWER GOOD (PG_LDO) PGOOD Threshold (Rising) PGOOD Threshold (Falling) PGOOD Output Voltage Low IOL = 1mA +11 -17 +15 -15 +18 -11 0.5 % % V CT = 0.01F Sink 1.0mA/Source 0.5mA at 0.4V from GND/VDD 2.68 2.7 0.4 25 2.79 2.77 20 0.54 2.81 2.79 0.7 V V mV A ms 2.3 1.0 V V 30 20 VRMS VRMS IOUT = 10mA VIN = 3.6V -1.5 200 250 -0.15 2.84 400 100 0.0 0.2 1.5 200 0.15 1.0 V % mA mA mV %/V % 65 60 VRMS VRMS IOUT = 10mA VIN = 3.6V -1.5 300 330 -0.15 -0.5 2.84 770 125 0.0 0.2 1.5 200 0.15 1.0 V % mA mA mV %/V % 1mA source/sink +5.5 -11.5 8.0 -8.0 +13 -5.5 % % Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V, Compensation Capacitors = 33nF for LDO1 and LDO2. TA = 25oC. (Note 2) (Continued) TEST CONDITIONS SYNC = GND or VIN MIN 20 TYP 0.01 MAX 0.15 80 UNITS A %
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ISL6413
Electrical Specifications
PARAMETER PGOOD Output Leakage Current PWM OUTPUT OVER VOLTAGE Over Voltage Threshold NOTE: 3. Specifications at -40oC and +85oC are guaranteed by design/characterization, not production tested. 4. This is the VIN current consumed when the device is active but not switching. Does not include gate drive current. 5. The dropout voltage is defined as VIN - VOUT, when VOUT is 50mV below the value of VOUT for VIN = VOUT + 0.5V. 6. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01F) the RESET time is 25ms; at 1000nF (0.1F) the RESET time would be 250ms. 7. Guaranteed by design, not production tested. 28 33 38 % VOUT = 3.3V Recommended operating conditions unless otherwise noted. VIN = VIN_LDO = PVCC = 3.3V, Compensation Capacitors = 33nF for LDO1 and LDO2. TA = 25oC. (Note 2) (Continued) TEST CONDITIONS MIN TYP 0.01 MAX 0.1 UNITS A
Typical Performance Curves
1V/DIV VIN
1V/DIV
0V VOUT1 0V 0V
1V/DIV
TIME (ms) (2ms/DIV)
TIME (s) (0.5s/DIV)
FIGURE 1. PWM SOFTSTART
FIGURE 2. PWM PHASE NODE SWITCHING
1.82
20mV/ DIV
PWM OUTPUT VOLTAGE
1.815
1.81
1.805
TIME (s) (2s/DIV)
1.8
0
0.05
0.1
0.15
0.2
0.25
0.3
LOAD CURRENT (A)
FIGURE 3. PWM OUTPUT RIPPLE WAVEFORMS
FIGURE 4. PWM LOAD REGULATION
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ISL6413 Typical Performance Curves (Continued)
1.816 1.814 PWM OUTPUT VOLTAGE 1.812 1.81 0V 1.808 1.806 1.804 1.802 2.7 VOUT1 1V/DIV VIN 1V/DIV
0V
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
INPUT VOLTAGE
FIGURE 5. PWM LINE REGULATION
FIGURE 6. PWM SHUTDOWN WITH VIN
VOUT VIN 1V/DIV 1V/DIV 0.5V/DIV 0V
VOUT2
0V
0V VOUT3
0V
0V
TIME (ms) (5ms/DIV)
FIGURE 7. PWM SHUTDOWN WITH EN_PWM
FIGURE 8. LDO SHUTDOWN WITH VIN
VOUT2 1V/DIV 0V
VOUT3 1V/DIV 0V
FIGURE 9. LDO SHUTDOWN WITH EN_LDO
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ISL6413 Pin Descriptions
PVCC - Positive supply for the power (internal FET) stage of the PWM section. SGND - Analog ground for the PWM. All internal control circuits are referenced to this pin. EN _PWM- The PWM controller is enabled when this pin is HIGH, and held off when the pin is pulled LOW. It is a CMOS logic-level input (referenced to VIN). VIN_LDO - This is the input voltage pin for LDO1 and LDO2. EN_LDO - LDO1 and LDO2 are enabled when this pin is HIGH, and held off when the pin is pulled LOW. It is a CMOS logic-level input (referenced to VIN). CT - Timing capacitor connection to set the 25ms minimum pulse width for the RESET/RESET signal. RESET, RESET - These complementary pins are the outputs of the reset supervisory circuit, which monitors VIN. The IC asserts these RESET and RESET signals whenever the supply voltage drops below a preset threshold; keeping them asserted for at least 25ms after VCC (VIN) has risen above the reset threshold. These outputs are push-pull. RESET is LOW when re-setting the microprocessor. The device will continue to operate until VIN drops below the UVLO threshold. PG_LDO - This is a high impedance open drain output that provides the status of both LDOs. When either of the outputs are out of regulation, PG_LDO goes LOW. CC1 - This is the compensation capacitor connection for LDO1. Connect a 0.033F capacitor from CC1 to GND_LDO. CC2 - This is the compensation capacitor connection for LDO2. Connect a 0.033F capacitor from CC2 to GND_LDO. VOUT2 - This pin is the output of LDO2. Bypass with a 2.2F, low ESR capacitor to GND_LDO for stable operation. GND_LDO - Ground pin for LDO1 and LDO2. VOUT1 - This pin is the output of LDO1. Bypass with a 2.2F, low ESR capacitor to GND_LDO for stable operation. PGND - Power ground for the PWM controller stage. VOUT - This I/O pin senses the output voltage of the PWM converter stage. For fixed 1.8V operation, connect this pin directly to the output voltage. PG_PWM - This pin is an active pull-up/pull-down able to source/sink 1mA (min.) at 0.4V from VIN/SGND. This output is HIGH when VOUT is within 8% (typ.). PG_PWM - This pin provides an inverted PG_PWM output. LX - The LX pin is the switching node of synchronous buck converter, connected internally at the junction point of the 8 upper MOSFET source and lower MOSFET drain. Connect this pin to the output inductor. VIN - This pin is the power supply for the PWM controller stage and must be closely decoupled to ground. SYNC - This is the external clock synchronization input. The device can be synchronized to 500kHz to 1MHz switching frequency. GND - Tie this pin to the ground plane with a low impedance, shortest possible path.
Functional Description
The ISL6413 is a 3-in-1 multi-output regulator designed for wireless chipset power applications. The device integrates a single synchronous buck regulator with dual LDOs. It supplies three fixed output voltages 1.8V, 2.84V and 2.84V. The 1.8V is generated using a synchronous buck regulator with greater then 92% efficiency. Both 2.84V supplies are generated from ultra low noise LDO Regulators. Under voltage lock-out (UVLO) prevents the converter from turning on when the input voltage is less then typically 2.6V Additional blocks include an output over-current protections, thermal sensor, PGOOD detectors, RESET function and shutdown logic.
Synchronous Buck Regulator
The Synchronous buck regulator with integrated N- and P-channel power MOSFET provides pre-set 1.8V for BBP/MAC core supply. Synchronous rectification with internal MOSFETs is used to achieve higher efficiency and reduced number of external components. Operating frequency is typically 750kHz allowing the use of smaller inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500kHz to 1MHz. The PG_PWM output indicates loss of regulation on PWM output. The PWM architecture uses a peak current mode control scheme with internal slope compensation. At the beginning of each clock cycle, the high side P-channel MOSFET is turned on. The current in the inductor ramps up and is sensed via an internal circuit. The error amplifier sets the threshold for the PWM comparator. The high side switch is turned off when the sensed inductor current reaches this threshold. After a minimum dead time preventing shoot through current, the low side N-channel MOSFET will be turned on and the current ramps down again. As the clock cycle is completed, the low side switch will be turned off and the next clock cycle starts. The control loop is internally compensated reducing the amount of external components. The PWM section includes an anti-ringing switch to reduce noise at light loads. The switch current is internally sensed and the minimum current limit is 600mA.
ISL6413
Synchronization
The typical operating frequency for the converter is 750kHz if no clock signal is applied to SYNC pin. It is possible to synchronize the converter to an external clock within a frequency range from 500kHz to 1000kHz. The device automatically detects the rising edge of the first clock and will synchronize immediately to the external clock. If the clock signal is stopped, the converter automatically switches back to the internal clock and continues operation without interruption. The switch over will be initiated if no rising edge on the SYNC pin is detected for a duration of two internal 1.3s clock cycles.
LDO Regulators
Each LDO consists of a 1.184V reference, error amplifier, MOSFET driver, P-Channel pass transistor, dual-mode comparator and internal feedback voltage divider. The 1.2V band gap reference is connected to the error amplifier's inverting input. The error amplifier compares this reference to the selected feedback voltage and amplifies the difference. The MOSFET driver reads the error signal and applies the appropriate drive to the P-Channel pass transistor. If the feedback voltage is lower then the reference voltage, the pass transistor gate is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher then the reference voltage, the pass transistor gate is driven higher, allowing less current to pass to the output. The output voltage is fed back through an internal resistor divider connected to VOUT1/VOUT2 pins.
Soft Start
As the EN_PWM (Enable) pin goes high, the soft-start function will generate an internal voltage ramp. This causes the start-up current to slowly rise preventing output voltage overshoot and high inrush currents. The soft-start duration is typically 5.5ms with 750kHz switching frequency. When the soft-start is completed, the error amplifier will be connected directly to the internal voltage reference. The SYNC input is ignored during soft start.
Internal P-Channel Pass Transistors
The ISL6413 LDO Regulators features a typical 0.5 Rds(ON) P-channel MOSFET pass transistors. This provides several advantages over similar designs using PNP bipolar pass transistors. The P-Channel MOSFET requires no base drive, which reduces quiescent current considerably. PNP based regulators waste considerable current in dropout when the pass transistor saturates. They also use high base drive currents under large loads. The ISL6413 does not suffer from these problems.
Enable PWM
Logic low on EN_PWM pin forces the PWM section into shutdown. In shutdown all the major blocks of the PWM including power switches, drivers, voltage reference, and oscillator are turned off.
Power Good (PG_PWM)
When chip is enabled, this output is HIGH, when VOUT is within 8% of 1.8V and active low outside this range. When the PWM is disabled, the output is active low. PG_PWM is the complement of PG_PWM. Leave the PG_PWM pin unconnected when not used.
Integrated RESET for MAC/ Baseband Processors
The ISL6413 includes a microprocessor supervisory block. This block eliminates the extra RESET IC and external components needed in wireless chipset applications. This block performs a single function; it asserts a RESET signal whenever the VIN supply voltage decreases below a preset threshold, keeping it asserted for a programmable time (set by external capacitor CT) after the VIN pin voltage has risen above the RESET threshold. The push pull output stage of the reset circuit provides both an active-Low and an active-HIGH output. The RESET threshold for ISL6413 is 2.630V typical. UVLO Reset threshold is always lower then RESET. This insures that as VIN falls, reset goes low before LDOs and PWM are shuts off.
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM cycle. Should it exceed the overcurrent limit, a 4 bit up/down counter counts up two LSB. Should it not be in overcurrent the counter counts down one LSB (but counter will not "rollover" or count below 0000). If >33% of the PWM cycles go into overcurrent, the counter rapidly reaches count 1111 and the PWM output is shut down and the softstart counter is reset. After 16 clocks the PWM output is enabled and the SS cycle is started. If VOUT exceeds the overvoltage limit for 32 consecutive clock cycles the PWM output is shut off and the SS counters reset. The softstart cycle will not be started until EN or VIN are toggled.
Output Voltages
The ISL6413 provides fixed output voltages for use in Wireless Chipset applications. Internal trimmed resistor networks set the typical output voltages as shown here: VOUT_PWM = 1.8V; VOUT1 = 2.84V; VOUT2 = 2.84V.
PG_LDO
PG_LDO is an open drain pulldown NMOS output that will sink 1mA at 0.4V max. It goes to the active low state if either LDO output is out of regulation by more than 15%. When the LDO is disabled, the output is active low. 9
Integrator Circuitry
The ISL6413 LDO Regulators uses an external 33nF compensation capacitor for minimizing load and line regulation errors and for lowering output noise. When the output voltage shifts due to varying load current or input
ISL6413
voltage, the integrator capacitor voltage is raised or lowered to compensate for the systematic offset at the error amplifier. Compensation is limited to 5% to minimize transient overshoot when the device goes out of dropout, current limit, or thermal shutdown. package by providing a direct heat conduction path from the die to the PC board. Additionally, the ISL6413's ground (GND_LDO and PGND) performs the dual function of providing an electrical connection to system ground and channeling heat away. Connect the exposed backside pad direct to the GND_LDO ground plane.
Shutdown
Driving the EN_LDO pin low will put LDO1 and LDO2 into the shutdown mode. Driving the EN_PWM pin low will put the PWM into shutdown mode. Pulling the EN_PWM and EN_LDO both pins low simultaneously, puts the complete chip into shutdown mode, and supply current drops to 15A typical.
Applications Information
LDO Regulator Capacitor Selection and Regulator Stability
Capacitors are required at the ISL6413 LDO Regulators' input and output for stable operation over the entire load range and the full temperature range. Use >1F capacitor at the input of LDO Regulators, VIN_LDO pins. The input capacitor lowers the source impedance of the input supply. Larger capacitor values and lower ESR provides better PSRR and line transient response. The input capacitor must be located at a distance of not more then 0.5 inches from the VIN pins of the IC and returned to a clean analog ground. Any good quality ceramic capacitor can be used as an input capacitor. The output capacitor must meet the requirements of minimum amount of capacitance and ESR for both LDO's. The ISL6413 is specifically designed to work with small ceramic output capacitors. The output capacitor's ESR affects stability and output noise. Use an output capacitor with an ESR of 50m or less to insure stability and optimum transient response. For stable operation, a ceramic capacitor, with a minimum value of 3.3F, is recommended for VOUT1 for 300mA output current, and 3.3F is recommended for VOUT2 at 200mA load current. There is no upper limit to the output capacitor value. Larger capacitor can reduce noise and improve load transient response, stability and PSRR. Higher value of output capacitor (10F) is recommended for LDO2 when used to power VCO circuitry in wireless chipsets. The output capacitor should be located very close to VOUT pins to minimize impact of PC board inductances and the other end of the capacitor should be returned to a clean analog ground.
Protection Features for the LDOs
Current Limit
The ISL6413 monitors and controls the pass transistor's gate voltage to limit the output current. The current limit for LDO1 is 330mA and LDO2 is 250mA. The output can be shorted to ground without damaging the part due to the current limit and thermal protection features.
Thermal Overload Protection
Thermal overload protection limits total power dissipation in the ISL6413. When the junction temperature (TJ) exceeds +150C, the thermal sensor sends a signal to the shutdown logic, turning off the pass transistor and allowing the IC to cool. The pass transistor turns on again after the IC's junction temperature typically cools by 20C, resulting in a pulsed output during continuous thermal overload conditions. Thermal overload protection protects the ISL6413 against fault conditions. For continuous operation, do not exceed the absolute maximum junction temperature rating of +150C.
Operating Region and Power Dissipation
The maximum power dissipation of ISL6413 depends on the thermal resistance of the IC package and circuit board, the temperature difference between the die junction and ambient air, and the rate of air flow. The power dissipated in the device is: PT = P1 + P2 + P3, where P1 = IOUT1 x VOUT1/IIN x VIN P2 = IOUT2 (VIN - VOUT2) P3 = IOUT3 (VIN- VOUT3) The maximum power dissipation is: Pmax = (Tjmax - TA)/JA Where Tjmax = 150oC, TA = ambient temperature, and JA is the thermal resistance from the junction to the surrounding environment. The ISL6413 package features an exposed thermal pad on its underside. This pad lowers the thermal resistance of the 10
PWM Regulator Component Selection
INDUCTOR SELECTION A 10H minimum output inductor is used with the ISL6413 PWM section. Values larger then 15H or less then 10H may cause stability problems because of the internal compensation of the regulator. The important parameters of the inductor that need to be considered are the current rating of the inductor and the DC resistance of the inductor. The dc resistance of the inductor will influence directly the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest efficiency.
ISL6413
In order to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current plus the inductor ripple current.
TABLE 1. RECOMMENDED INDUCTORS OUTPUT INDUCTOR CURRENT VALUE 0mA to 600mA 10H VENDOR PART # COMMENTS
INPUT CAPACITOR SELECTION Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The input capacitor should have a minimum value of 10F and can be increased without any limit for better input voltage filtering. The input capacitor should be rated for the maximum input ripple current calculated as:
VO V O I RMS = I O ( max ) x ------- x 1 - ------- VI VI
Coilcraft DO3316P-103 High Efficiency Coilcraft DT3316P-103 Sumida CDR63B-100 Sumida CDRH5D28-100 Coilcraft DO1608C-100 Smallest Sumida CDRH4D28-100 Solution
0mA to 300mA
10H
Coilcraft DS1608C-103 Murata LQH4C100K04
High Efficiency Smallest Solution
The worst case RMS ripple current occurs at D = 0.5. Ceramic capacitors show good performance because of their low ESR value, and because they are less sensitive to voltage transients, compared to tantalum capacitors. Place the input capacitor as close as possible to the input pin of the IC for best performance.
OUTPUT CAPACITOR SELECTION For best performance, a low ESR output capacitor is needed. If an output capacitor is selected with an ESR value 120m, its RMS ripple current rating will always meet the application requirements. The RMS ripple current is calculated as:
VO 1 - ------VI 1 I RMS ( C ) = V O x ----------------- x ---------------Lxf O 2x 3
Layout Considerations
As for all switching power supplies, the layout is an important step in the design especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Use a common ground node to minimize the effects of ground noise. Allocate two board levels as ground planes, with many vias between them to create a low impedance, high-frequency plane. Tie all the device ground pins through multiple vias each to this ground plane, as close to the device as possible. Also tie the exposed pad on the bottom of the device to this ground plane. Refer to application note AN1081.
The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charge and discharging the output capacitor:
1 - V O ------- VI 1 V O = V O x ----------------- x ------------------------- + ESR L x f 8 x C x f O
Where the highest output voltage ripple occurs at the highest input voltage VI.
TABLE 2. RECOMMENDED CAPACITORS CAPACITOR VALUE 10F 47F 68F ESR/m 50 100 100 VENDOR PART # Taiyo Yuden JMK316BJ106KL Sanyo 6TPA47M Sprague 594D686X0010C2T COMMENTS Ceramic POSCAP Tantalum
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ISL6413 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L24.4x4B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-2 ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 2.19 2.19 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 4.00 BSC 3.75 BSC 2.34 4.00 BSC 3.75 BSC 2.34 0.50 BSC 0.40 24 6 6 0.60 12 0.50 0.15 2.49 2.49 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 0 10/03 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12

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